Assignment 1: Implementation of AND, OR, NOT, XOR, NAND, NOR gates using Xilinx ISE.
Aim:
Objective: To implement OR gate
Software used: edaplayground
Top-level source type | HDL |
Synthesis Tool | VHDL/verilog |
Simulator | Aldec Riviera Pro |
Preferred Language | VHDL |
Theory:
An OR gate has two or more than two inputs and one output signal. It is called an OR gate because the output signal will be high only if any or all input signals are high.
Truth Table:
INPUT | OUTPUT | |
A | B | Y |
0 | 0 | 0 |
0 | 1 | 1 |
1 | 0 | 1 |
1 | 1 | 1 |
Behavioral Model:
Data flow Model:
Behavioral Model Code:
library IEEE;
use IEEE.std_logic_1164.all;
entity OR_gate is port (
a: in std_logic; b: in std_logic; c: out std_logic;
);
end OR_gate;
architecture myarch of OR_gate is begin
process (a,b)
begin
if(a=’0’ and b=’0’) then c<=’0’;
else c<=’1’;
end if;
end process; end myarch;
Data flow Model Code:
library IEEE;
use IEEE.std_logic_1164.all;
entity OR_gate is port (
a: in std_logic; b: in std_logic; c: out std_logic;
);
end OR_gate;
architecture myarch of OR_gate is begin
c<= a and b; end myarch;
Output:
Objective: To implement AND gate
Software used: edaplayground
Top-level source type | HDL |
Synthesis Tool | VHDL/verilog |
Simulator | Aldec Riviera Pro |
Preferred Language | VHDL |
Theory:
An AND gate is a logic gate having two or more inputs and a single output. An AND gate operates on logical multiplication rules. In this gate, if either of the inputs is low (0), then the output is also low. If all of the inputs are high (1), then the output will also be high.
Truth Table:
INPUT | OUTPUT | |
A | B | Y |
0 | 0 | 0 |
0 | 1 | 0 |
1 | 0 | 0 |
1 | 1 | 1 |
Behavioral Model:
Data flow Model:
Code:
Behavioral Model Code:
library IEEE;
use IEEE.std_logic_1164.all;
entity AND_gate is port (
a: in std_logic; b: in std_logic; c: out std_logic;
);
end AND_gate;
architecture myarch of AND_gate is begin
process(a,b) begin
if(a=’1’ and b=’1’) then c<=’1’;
else c<=’0’;
end if;
end process; end myarch;
Data flow Model Code:
library IEEE;
use IEEE.std_logic_1164.all;
entity AND_gate is port (
a: in std_logic; b: in std_logic; c: out std_logic;
);
end AND_gate;
architecture myarch of AND_gate is begin
c<= a and b; end myarch;
Output:
Objective: To implement NOT gate
Software used: edaplayground
Top-level source type | HDL |
Synthesis Tool | VHDL/verilog |
Simulator | Aldec Riviera Pro |
Preferred Language | VHDL |
Theory:
The NOT gate is a single input single output gate. This gate is also known as Inverter because it performs the inversion of the applied binary signal, i.e., it converts 0 into 1 or 1 into 0.
Truth Table:
INPUT | OUTPUT |
A | Y |
0 | 1 |
1 | 0 |
Behavioral Model:
Data flow Model:
Code:
Behavioral Model Code:
library IEEE;
use IEEE.std_logic_1164.all; entity NOT_gate is
port (
a: in std_logic; c: out std_logic;
);
end NOT_gate;
architecture behave of NOT_gate is begin
process(X)
begin if(x=’0’) then
c <= ‘1’;
else
c <= ‘0’;
end if;
end process; end myarch;
Data flow Model Code:
library IEEE;
use IEEE.std_logic_1164.all; entity NOT_gate is
port (
a: in std_logic; c: out std_logic;
);
end NOT_gate;
architecture myarch of NOT_gate is begin
c<= not a; end myarch
Output:
Objective: To implement NOR gate
Software used: edaplayground
Top-level source type | HDL |
Synthesis Tool | VHDL/verilog |
Simulator | Aldec Riviera Pro |
Preferred Language | VHDL |
Theory: An OR gate followed by a NOT gate in a cascade is called a NOR gate. In other words, the gate which provides a high output signal only when there are low signals on the inputs such type of gate is known as NOR gate.
Truth Table:
INPUT | OUTPUT | |
A | B | Y |
0 | 0 | 1 |
0 | 1 | 0 |
1 | 0 | 0 |
1 | 1 | 0 |
Behavioral Model:
Data flow Model:
Behavioral Model Code:
library IEEE;
use IEEE.std_logic_1164.all;
entity NOR_gate is port (
a: in std_logic; b: in std_logic; c: out std_logic;
);
end NOR_gate;
architecture myarch of NOR_gate is begin
process(a,b) begin
if(a=’0’ and b=’0’) then c<=’1’;
else c<=’0’;
end if;
emd process; end myarch;
Data flow Model Code:
library IEEE;
use IEEE.std_logic_1164.all;
entity NOR_gate is port (
a: in std_logic; b: in std_logic; c: out std_logic;
);
end NOR_gate;
architecture myarch of NOR_gate is begin
c<= a nor b; end myarch;
Output:
Objective: To implement NAND gate
Software used: edaplayground
Top-level source type | HDL |
Synthesis Tool | VHDL/verilog |
Simulator | Aldec Riviera Pro |
Preferred Language | VHDL |
Theory: It is a combination of AND and NOT gates and is a commonly used logic gate. It is considered as a "universal" gate in Boolean algebra as it is capable of producing all other logic gates. A NAND gate consists of one or more inputs with a single output. The output of the NAND gate is always at logic 1 and only goes to logic 0 when all the inputs to the NAND gate are at logic 1.
Truth Table:
INPUT | OUTPUT | |
A | B | Y |
0 | 0 | 1 |
0 | 1 | 1 |
1 | 0 | 1 |
1 | 1 | 0 |
Behavioral Model:
Data flow Model:
Code:
Behavioral Model Code:
library IEEE;
use IEEE.std_logic_1164.all;
entity NAND_gate is port (
a: in std_logic; b: in std_logic; c: out std_logic;
);
end NAND_gate;
architecture myarch of NAND_gate is begin
process(a,b)
if(a=’1’ and b=’1’) then c<=’0’;
else c<=’1’;
end if;
end process; end myarch;
Data flow Model Code:
library IEEE;
use IEEE.std_logic_1164.all;
entity NAND_gate is port (
a: in std_logic; b: in std_logic; c: out std_logic;
);
end NAND_gate;
architecture myarch of NAND_gate is begin
c<= a nand b; end myarch;
Output:
Objective: To implement XOR gate
Software used: edaplayground
Top-level source type | HDL |
Synthesis Tool | VHDL/verilog |
Simulator | Aldec Riviera Pro |
Preferred Language | VHDL |
Theory:
An XOR gate is a digital logic gate with two or more inputs and one output that performs exclusive disjunction. The output of an XOR gate is true only when exactly one of its inputs is true. If both of an XOR gate's inputs are false, or if both of its inputs are true, then the output of the XOR gate is false.
Truth Table:
INPUT | OUTPUT | |
A | B | Y |
0 | 0 | 0 |
0 | 1 | 1 |
1 | 0 | 1 |
1 | 1 | 0 |
Behavioral Model:
Data flow Model:
Code:
Behavioral Model Code:
library IEEE;
use IEEE.std_logic_1164.all;
entity XOR_gate is port (
a: in std_logic; b: in std_logic; c: out std_logic;
);
end XOR_gate;
architecture myarch of XOR_gate is begin
possess(a,b)
begin if(a/=b) then c<=’1’;
else c<=’0’;
end if;
end process; end myarch;
Data flow Model Code:
library IEEE;
use IEEE.std_logic_1164.all;
entity XOR_gate is port (
a: in std_logic;
b: in std_logic; c: out std_logic;
);
end XOR_gate;
architecture myarch of XOR_gate is begin
c<= a xor b; end myarch
Output:
Discussion :
In this experiment we have implemented OR, AND, NOT, NAND, NOR AND XOR gates in edaplayground in the behavioral and data flow model using VHDL technique.
VHDL CODE WITH TESTBENCH
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